FIG. 1 shows part of a conventional SDRAM 10. As shown, the SDRAM 10 has multiple, i.e., N memory arrays 11 and 12 although only two memory arrays are shown for sake of clarity. As in an ordinary DRAM, the memory cells of each memory array 11 and 12 are arranged into a two-dimensional "super" memory array of rows and columns, of which each memory array 11 and 12 is simply a sub-array (each memory array 11, 12 containing only a subset of the columns of the super memory array). A particular memory cell can be accessed by activating a row line of a row of the accessed memory cell and a column line, or pair of column lines of a column of the accessed memory cell. Herein, each column of cells is assumed to be connected to a pair of column lines without loss of generality. The access can be in the form of a read or write operation, and a row line or pair of column lines can be activated by applying a particular voltage to the line or pair of lines or monitoring a voltage on the particular line or pair of lines. Each memory cell is assigned a unique address which can be divided into a row address portion and a column address portion. The row address portion indicates a particular row line to activate, and the column address portion specifies a particular pair of column lines to activate, when accessing the memory cell.
Like an ordinary DRAM, the SDRAM 10 supports ordinary read and write operations, during which only a single addressed memory cell is accessed at one time. However, the SDRAM 10 also supports a synchronous write operation and a synchronous read operation during which multiple cells in the same row are accessed in rapid succession. A number of different techniques may be employed to effect such successive rapid accesses. See H. J Yoo, A Study of Pipeline Architectures for High-Speed Synchronous DRAM's, IEEE J. SOLIDSTATE CIRS., vol. 32, no. 10, October, 1997, page 1597-1603. The particular SDRAM 10 shown in FIG. 1 uses a prefetch technique to effect several accesses in rapid succession. According to a prefetch technique, a single row line, and multiple column lines are simultaneously activated in order to cause multiple memory cells to be accessed simultaneously. In the case of a prefetch read, multiple memory cells, including one memory cell in each bank 11 and 12, simultaneously output the data values that they store onto a respective column line pair 13 or 14. The data values are outputted simultaneously via column selectors 15 and 16 onto a respective I/O line pair 17 or 18. Data sense amplifiers 19 and 20 receive the signals on I/O lines 17 and 18 from the column selectors 15 and 16 and simultaneously output the sensed data signals on the read/write line pairs 21 or 22 corresponding to the memory array 11 or 12, respectively, to which each respective data sense amplifier 19 or 20 is connected. The data values on read/write line pairs 21 or 22 are each simultaneously received at, and simultaneously stored in, a respective latch 23 or 24 to which each read/write line pair 21 or 22 is connected. Each latch 23 or 24 outputs the data value stored therein depending on a respective control or clock signal SFCLK0 or SFCLK1. Illustratively, these control signals have enabling pulses that occur in rapid succession so as to sequentially output the data value in latch 23 followed by the data value in latch 24. This is shown in FIG. 2 for a general case of outputting N total data values from N memory arrays 11 and 12. Each control signal SFCLK0, SFCLK1, . . . SFCLKN-1 is generated in succession during a respective n.sup.th (1.ltoreq.n.ltoreq.N) interval of a transfer cycle having a duration of 1/N of the length of the transfer cycle. The sequentially outputted data values are amplified by driver 25 and then driven onto the DQ pad 26 in succession.
During a prefetch write operation, a sequence of data values are received in rapid succession at DQ pad 26. Each signal of the sequence is amplified by driver 25 and fed to the latches 23 and 24. Control signals SFCLK0 and SFCLK1 are provided with enabling pulses that occur in rapid succession; the enabling pulse of SFCLK0 occurring when the data value of the sequence to be stored in memory array 11 is applied to DQ pad 26 and the enabling pulse of SFCLK1 occurring when the data value of the sequence to be stored in memory array 12 is applied to the DQ pad. Such enabling pulses also occur during corresponding n.sup.th intervals of the transfer cycle as shown in FIG. 2. After each data value is stored in its respective latch 23 or 24, the data values are simultaneously outputted via corresponding read/write line pairs 21 or 22 attached to the latch 23 or 24, respectively, through data sense amplifiers 19 or 20, respectively and onto I/O lines 17 or 18, respectively. From there, the corresponding column selector 15 or 16 outputs the data values onto the column line pair 13 or 14 for storage in the appropriate memory array 11 or 12, respectively.
One of the problems with the SDRAM 10 is that the read/write lines 21 and 22 take up a large amount of area on the IC chip, represented in FIG. 1 by the width w and length l. Here, l is approximately equal to the distance from the data sense amplifier of the memory array most distant from the latches 23, 24 to the latches 23 and 24. The length l is a function of the number of memory arrays 11 and 12 and the length of each memory array 11 and 12. Generally speaking, the line spacing (line width and inter-line spacing) requirement is 2 .mu.m. If there are 32 memory arrays, and two read/write lines (for differential signal transmission) per memory array, then 64 lines with a total width requirement of w=128 .mu.m is needed. In such a case, the area needed for the read/write lines is 128.times.1 .mu.m.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.